The present invention relates to systems and methods for addressing memory locations and, more particularly, to systems and methods for dynamically accessing a memory as a linear memory space and as a dual memory space.
Digital Signal Processors (DSPs) conventionally are structured to perform mathematical calculations very quickly. The calculations may include repetitive operations such as multiply and accumulate operations that are performed on a series of constant or calculated data stored in a memory. For optimum performance, DSPs must be able to repetitively fetch two operands for immediate processing, calculate a result and write the result back within one processor cycle. In pipelined implementations, result write back should occur at the end of each processor cycle once the pipeline is full.
To allow DSPs to show significant performance improvement over conventional processors for the above types of operations, DSPs typically have the ability to perform dual concurrent operand fetches from a relatively large data memory. Conventional micro-controllers and microprocessors typically allow dual concurrent operand fetches only from a limited number registers, which is overly restrictive for DSPs. This is because processor cycles must be devoted to loading registers with operand data as an intermediate step prior to processing the data, rather than fetching the operand data directly from the memory in the case of a DSP.
Conventional DSPs typically include two data memories, an X memory and a Y memory. They further include X and Y data buses coupled respectively to the X and Y memories. The X and Y memories are separately addressed and allow the DSP to perform dual, concurrent operand fetching and processing directly from the memoriesxe2x80x94one operand being fetched from the X memory and the other from the Y memory.
Providing separate X and Y memories with separate busing structures allows conventional DSPs to efficiently execute instructions on two operands. However, for instructions that do not require two operands, as is the case for typical micro controller unit (MCU) or non-DSP instructions, separate X and Y memories may be a disadvantage. This is because operands may be stored in either the X or the Y memory. Accordingly, programmers must keep track of which memory the operand data is stored in to retrieve the proper data.
Accordingly, there is a need for a more efficient memory organization for digital signal processing which permits good MCU or non-DSP instruction support. There is a further need for a memory organization that provides dual concurrent operand fetching for DSP class instructions but which allows access to all memory locations when single operands are required without requiring software overhead to track whether the operand is in the X or Y memory and without requiring separate read instructions.
According to the present invention, a processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.
According to an embodiment of the invention, the method provides linear and dual address spaces within a memory. The method includes providing a digital signal processor (DSP) engine, an arithmetic logic unit (ALU) and a memory. The method further includes providing separate X and Y address generation units for generating addresses to the memory. The X address generation unit may be configured to generate addresses to all of the memory space when processing a non-digital signal processor (DSP) engine instruction and to a first portion of the memory when processing a DSP engine instruction. The Y address generation unit may be configured to generate addresses to a second portion of the memory space when processing a DSP engine instruction and to none of the memory space when processing a non-digital signal processor (DSP) engine instruction. The method may further include providing an instruction decoder that decodes instructions and, in response, activates the X address generation unit for ALU instructions and activates the X and Y address generation units for DSP engine instructions. The first and second memory portions may be overlapping or non-overlapping. The first and second portion memory portions may further be contiguous or not contiguous with respect to each other. In addition, the first portion may include a portion above the second portion and a portion below the second portion.
According to another embodiment, the method may further include providing separate X and Y data buses. In this configuration, the X data bus may be coupled to the memory permitting reading and writing to and from the entire memory and the Y data bus may be coupled to the second portion of the memory permitting reading and also writing in some embodiments from the second portion. The method may further include reading X and Y operands concurrently from the respective first and second portions of the memory over the X and Y data buses based on the instruction decoder decoding a DSP instruction requiring a dual operand fetch.
According to another embodiment of the invention, a processor addresses a memory as a single and dual space memory based on an addressing mode. The processor includes a data memory, an instruction decoder and X and Y address generators. The data memory has X and Y memory spaces. The instruction decoder determines whether an instruction requires single or dual memory space operation and selectively activates the X and Y address generators. The instruction decoder activates the X and Y address generators based on the instruction decoder determining dual memory space operation is required. Alternatively, the instruction decoder activates the X address generator only based on the instruction decoder determining single memory space operation is required.
The processor may further include registers coupled to the X and Y address generators for storing pointers to the memory. For a dual memory space operation, a subset of the registers stores pointers to the Y space within the memory and a subset of the registers stores pointers to the X space within the memory. For a single memory space operation, any of the registers stores pointers to the memory.
The processor may further include X and Y data buses coupled to the memory for retrieving operands from the X and Y memory spaces in a dual memory space operation and for retrieving operands from the memory over the X data bus in a single memory space operation. The processor may further include a DSP engine having operand inputs coupled to the X and Y data buses and having a result output coupled only to the X data bus. The processor may still further include an arithmetic logic unit (ALU) coupled to the X data buses for operand and result input and output.